A semiconductor chip including a termination resistance and a semiconductor module including the semiconductor chip. The semiconductor chip comprising a plurality of memory cells, the semiconductor chip including: at least one first center pads disposed on a center region of the semiconductor chip and connected to the plurality of memory cells; at least one first edge pads disposed on an edge region of the semiconductor chip and connected to a first transmission line of a semiconductor module; at least one second edge pads disposed on the edge region of the semiconductor chip and connected to a chipset voltage application unit of the semiconductor module; at least one first redistribution patterns connected between the at least one first center pads and the at least one first edge pads; and at least one second redistribution patterns connected between the at least one first edge pads and the at least one second edge pads, wherein an impedance of the at least one second redistribution patterns is impedance matched to an impedance of the first transmission line.