In a counter circuit of a control signal generating circuit, a selector circuit selects under control which is in accordance with a selector circuit control signal (CTR) a predetermined one in a signal VSYNC and a signal HSYNC, which are pulse signals, so as to input a pulse signal thus selected to a counter. The counter outputs a counted result of pulses of the inputted pulse signal. By use of the counted result, a VSYNC synchronization signal generating circuit or an HSYNC synchronization signal generating circuit generates a control signal to control the driving of image display.