Invention Grant
- Patent Title: PLC-type delay demodulation circuit
- Patent Title (中): PLC型延时解调电路
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Application No.: US13333432Application Date: 2011-12-21
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Publication No.: US08422118B2Publication Date: 2013-04-16
- Inventor: Hiroshi Kawashima , Kazutaka Nara
- Applicant: Hiroshi Kawashima , Kazutaka Nara
- Applicant Address: JP Tokyo
- Assignee: Furukawa Electric Co., Ltd.
- Current Assignee: Furukawa Electric Co., Ltd.
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-077634 20100330
- Main IPC: G02F2/00
- IPC: G02F2/00

Abstract:
A PLC-type delay demodulation circuit includes a planar lightwave circuit that is provided on one PLC chip and demodulates a DQPSK signal. The planar lightwave circuit includes a Y-branch waveguide that branches a DQPSK-modulated optical signal into two optical signals and first and second MZIs that delay the branched optical signals by one bit. The length of a short arm waveguide of the first MZI is different from the length of a short arm waveguide of the second MZI, and the length of an optical path from the Y-branch waveguide to output ports of the first MZI through the short arm waveguide of the first MZI is equal to that of an optical path from the Y-branch waveguide to output ports of the second MZI through the short arm waveguide of the second MZI.
Public/Granted literature
- US20120154901A1 PLC-TYPE DELAY DEMODULATION CIRCUIT Public/Granted day:2012-06-21
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