Invention Grant
- Patent Title: System and method for gate training in a memory system
- Patent Title (中): 存储系统中门训练的系统和方法
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Application No.: US13118499Application Date: 2011-05-30
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Publication No.: US08422319B2Publication Date: 2013-04-16
- Inventor: Srinivas Sriadibhatla , Curtis Matheson Webster
- Applicant: Srinivas Sriadibhatla , Curtis Matheson Webster
- Applicant Address: US CA San Jose
- Assignee: LSI Corporation
- Current Assignee: LSI Corporation
- Current Assignee Address: US CA San Jose
- Agency: Mendelsohn, Drucker & Associates, P.C.
- Agent Steve Mendelsohn
- Main IPC: G11C7/00
- IPC: G11C7/00

Abstract:
A system and method for gate training in a memory system is disclosed. In one embodiment, in a method for calibrating read data strobe gating, a first read command is issued to a memory module. A first DQS gate signal is issued before the beginning of the preamble of a first DQS signal received from the memory module that corresponds to the first read command. A second read command is issued to the memory module such that the preamble of a second DQS signal received from the memory module that corresponds to the second read command is adjacent to the postamble of the first DQS signal. Then, a second DQS gate signal is issued at a preset time after the first DQS gate signal. The second DQS signal is sampled repeatedly to locate the preamble of the second DQS signal.
Public/Granted literature
- US20120307577A1 SYSTEM AND METHOD FOR GATE TRAINING IN A MEMORY SYSTEM Public/Granted day:2012-12-06
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