Invention Grant
US08422619B2 Clock frequency divider circuit, clock distribution circuit, clock frequency division method, and clock distribution method 有权
时钟分频电路,时钟分配电路,时钟分频方式和时钟分配方式

  • Patent Title: Clock frequency divider circuit, clock distribution circuit, clock frequency division method, and clock distribution method
  • Patent Title (中): 时钟分频电路,时钟分配电路,时钟分频方式和时钟分配方式
  • Application No.: US13058463
    Application Date: 2009-07-30
  • Publication No.: US08422619B2
    Publication Date: 2013-04-16
  • Inventor: Atsufumi Shibayama
  • Applicant: Atsufumi Shibayama
  • Applicant Address: JP Tokyo
  • Assignee: NEC Corporation
  • Current Assignee: NEC Corporation
  • Current Assignee Address: JP Tokyo
  • Priority: JP2008-278497 20081029
  • International Application: PCT/JP2009/003631 WO 20090730
  • International Announcement: WO2010/050097 WO 20100506
  • Main IPC: H03K21/00
  • IPC: H03K21/00
Clock frequency divider circuit, clock distribution circuit, clock frequency division method, and clock distribution method
Abstract:
To provide a clock frequency divider circuit that generates a clock signal enabling an expected proper communication in communication with a circuit operating by a clock having a different frequency. A clock frequency division circuit according to the present invention generates an output clock signal obtained by dividing a frequency of an input clock signal into N/S by subtracting (S−N) clock pulses from S clock pulses of the input clock signal based on a frequency division ratio defined as N/S. The clock frequency division circuit generates a control signal used to preferentially subtract a clock pulse at a timing other than a communication timing of data communication performed by a target circuit using the output clock signal among S clock pulses of the input clock signal. Further, it generates the output clock signal by subtracting a clock pulse of the input clock signal according to the generated control signal.
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