Invention Grant
- Patent Title: Simulation parameter extracting method of MOS transistor
- Patent Title (中): MOS晶体管的仿真参数提取方法
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Application No.: US12969256Application Date: 2010-12-15
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Publication No.: US08423342B2Publication Date: 2013-04-16
- Inventor: Yasuhisa Naruta
- Applicant: Yasuhisa Naruta
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Sughrue Mion, PLLC
- Priority: JP2009-284850 20091216
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A simulation parameter extracting method of a MOS transistor according to an exemplary aspect of the present invention includes evaluating a measured value that includes a true gate-overlap capacitance by measuring a capacitance between the gate and the drain in each of a plurality of layout patterns at a predetermined bias voltage, only the number of contact plugs being different for each layout pattern, evaluating a gate-overlap capacitance calculation value of each layout pattern by subtracting a contact parasitic capacitance between the contact plug and the gate from the measured value, the contact parasitic capacitance being obtained by a simulation with varying a model parameter for evaluating a parasitic capacitance between the contact plug and the gate, and extracting the gate-overlap capacitance calculation value as the true gate-overlap capacitance at the model parameter when the gate-overlap capacitance calculation value is about constant regardless of the number of the contact plugs.
Public/Granted literature
- US20110144968A1 SIMULATION PARAMETER EXTRACTING METHOD OF MOS TRANSISTOR Public/Granted day:2011-06-16
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