An apparatus includes a processor which issues a plurality of commands including an identifier for classifying each of the commands, a cache memory which includes a plurality of ways to store a data corresponding to a command, wherein the cache memory includes a register to store the identifier, the register corresponding to at least one of the ways being fixed, the fixed way exclusively storing the data corresponding to the identifier during which the register stores the identifier, a replacement controller which selects a replacement way based on a predetermined replacement algorithm in case of a cache miss, and excludes the fixed way from a candidate of the replacement way when the register corresponding to the fixed way stores the identifier.