A computer system includes a CPU, a memory circuit storing at least instruction codes, an error checking circuit checking an error of an instruction code read from the memory circuit according to an instruction address supplied from the CPU, a code storing circuit storing data to be outputted to the CPU instead of data from the memory when an error occurs, a selection circuit in which inputs are coupled to the memory circuit and the code storing circuit, and selectively outputting data from the code storing circuit when an error is detected by the error checking circuit, a bus connecting the selection circuit to the CPU, and an instruction error register storing a value indicating that an error occurs when the error is detected by the error checking circuit.