Invention Grant
US08423843B2 Method and system thereof for optimization of power consumption of scan chains of an integrated circuit for test 有权
用于优化用于测试的集成电路的扫描链的功耗的方法和系统

  • Patent Title: Method and system thereof for optimization of power consumption of scan chains of an integrated circuit for test
  • Patent Title (中): 用于优化用于测试的集成电路的扫描链的功耗的方法和系统
  • Application No.: US12910510
    Application Date: 2010-10-22
  • Publication No.: US08423843B2
    Publication Date: 2013-04-16
  • Inventor: David Allen
  • Applicant: David Allen
  • Applicant Address: US CA San Jose
  • Assignee: Atrenta, Inc.
  • Current Assignee: Atrenta, Inc.
  • Current Assignee Address: US CA San Jose
  • Agency: Sughrue Mion, PLLC
  • Main IPC: G01R31/28
  • IPC: G01R31/28
Method and system thereof for optimization of power consumption of scan chains of an integrated circuit for test
Abstract:
Scan blocks with scan chains are used to partition and test semiconductor devices using scan groups. The partitioning of the semiconductor device enables testing of all elements within each scan block, at speed, to provide fault coverage. A challenge in scan testing is keeping the power dissipation during testing under the allowed power capabilities of the tester power supplies, as the power used during scan test is much higher than that used during functional testing. A method for estimating the power dissipation of scan blocks in a circuit during the design stage is disclosed. Using the results generated, the circuit designer divides the design into an optimum number of scan blocks for test. Thus at-speed scan of the individual or groups of scan blocks can be estimated, during design, for optimizing test time while keeping the test power within acceptable limits.
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