Invention Grant
US08423845B2 On-chip logic to log failures during production testing and enable debugging for failure diagnosis
有权
在生产测试期间记录故障的片上逻辑，并启用故障诊断调试
- Patent Title: On-chip logic to log failures during production testing and enable debugging for failure diagnosis
- Patent Title (中): 在生产测试期间记录故障的片上逻辑，并启用故障诊断调试
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Application No.: US12629036Application Date: 2009-12-01
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Publication No.: US08423845B2Publication Date: 2013-04-16
- Inventor: Friedrich Hapke , Juergen Schloeffel , Michael Wittke , Rene Krenz-Baath
- Applicant: Friedrich Hapke , Juergen Schloeffel , Michael Wittke , Rene Krenz-Baath
- Applicant Address: US OR Wilsonville
- Assignee: Mentor Graphics Corporation
- Current Assignee: Mentor Graphics Corporation
- Current Assignee Address: US OR Wilsonville
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
On-chip logic includes a shadow register cross-coupled with a multiple input shift/signature register (MISR). The shadow register facilitates debugging by shifting out a test signature while resetting the MISR with a fault-free signature. The on-chip logic may further include comparator circuitry to produce an output signal by comparing the test signature with the fault-free signature or by first compressing the test signature and then comparing the compressed test signature with the compressed fault-free signature.
Public/Granted literature
- US20110047425A1 On-Chip Logic To Log Failures During Production Testing And Enable Debugging For Failure Diagnosis Public/Granted day:2011-02-24
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