Invention Grant
US08423878B2 Memory controller and memory system including the same having interface controllers generating parity bits
有权
包括具有产生奇偶校验位的接口控制器的存储器控制器和存储器系统
- Patent Title: Memory controller and memory system including the same having interface controllers generating parity bits
- Patent Title (中): 包括具有产生奇偶校验位的接口控制器的存储器控制器和存储器系统
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Application No.: US12758103Application Date: 2010-04-12
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Publication No.: US08423878B2Publication Date: 2013-04-16
- Inventor: WooSeong Cheong , Bumseok Yu , Chanho Yoon
- Applicant: WooSeong Cheong , Bumseok Yu , Chanho Yoon
- Applicant Address: KR Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si, Gyeonggi-do
- Agency: Volentine & Whitt, PLLC
- Priority: KR10-2009-0047105 20090528
- Main IPC: G06F11/00
- IPC: G06F11/00
Abstract:
A memory controller includes first and second interface controllers configured to exchange data with external devices, and an internal block connected between the first and second interface controllers. The first and second interface controllers exchange data received from the external devices and at least one parity bit corresponding to the received data through the internal block.
Public/Granted literature
- US20100306631A1 MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME Public/Granted day:2010-12-02
Information query
