Invention Grant
US08423938B2 Wire spacing verification method, wire spacing verification apparatus, and computer-readable medium 失效
线间隔验证方法,线间隔验证装置和计算机可读介质

  • Patent Title: Wire spacing verification method, wire spacing verification apparatus, and computer-readable medium
  • Patent Title (中): 线间隔验证方法,线间隔验证装置和计算机可读介质
  • Application No.: US13074330
    Application Date: 2011-03-29
  • Publication No.: US08423938B2
    Publication Date: 2013-04-16
  • Inventor: Daita Tsubamoto
  • Applicant: Daita Tsubamoto
  • Applicant Address: JP Kawasaki
  • Assignee: Fujitsu Limited
  • Current Assignee: Fujitsu Limited
  • Current Assignee Address: JP Kawasaki
  • Agency: Staas & Halsey LLP
  • Priority: JP2010-80271 20100331
  • Main IPC: G06F17/50
  • IPC: G06F17/50 G06F9/455
Wire spacing verification method, wire spacing verification apparatus, and computer-readable medium
Abstract:
A wire-spacing verification method for a computer includes calculating a characteristic impedance of each wire model disposed in a substrate model on a basis of a propagation rate of a signal in the wire model and rise time or fall time of an element model for transmitting the signal, calculating a reference impedance for predetermined sections, creating a distribution map in a direction of a section length with respect to the characteristic impedance of each of the sections for which the reference impedance is calculated, calculating an index indicating a degree of mismatch with the reference impedance, on a basis of the created distribution map, and making an approval/denial determination on the wire model on a basis of the index.
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