Invention Grant
- Patent Title: Reducing resistivity in interconnect structures of integrated circuits
- Patent Title (中): 降低集成电路互连结构中的电阻率
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Application No.: US13036599Application Date: 2011-02-28
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Publication No.: US08426307B2Publication Date: 2013-04-23
- Inventor: Cheng-Lin Huang
- Applicant: Cheng-Lin Huang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.
Public/Granted literature
- US20110171826A1 Reducing Resistivity in Interconnect Structures of Integrated Circuits Public/Granted day:2011-07-14
Information query
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