Invention Grant
- Patent Title: Laminated semiconductor substrate, laminated chip package and method of manufacturing the same
- Patent Title (中): 层叠半导体衬底,层压芯片封装及其制造方法
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Application No.: US12801837Application Date: 2010-06-28
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Publication No.: US08426946B2Publication Date: 2013-04-23
- Inventor: Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima
- Applicant: Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima
- Applicant Address: US CA Milpitas CN Hong Kong
- Assignee: Headway Technologies, Inc.,SAE Magnetics (H.K.) Ltd.
- Current Assignee: Headway Technologies, Inc.,SAE Magnetics (H.K.) Ltd.
- Current Assignee Address: US CA Milpitas CN Hong Kong
- Agency: Oliff & Berridge, PLC
- Main IPC: H01L23/02
- IPC: H01L23/02

Abstract:
In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein, a first wiring electrode and a second wiring electrode extend to the inside of a interposed groove part from a first device region and a second device region respectively, and are separated from each other. In the laminated semiconductor substrate, a through hole which the first wiring electrode appears is formed. The laminated semiconductor substrate has a through electrode. The through electrode is contact with all of the first wiring electrodes appearing in the through hole. The laminated semiconductor substrate has a plurality of laminated chip regions.
Public/Granted literature
- US20110316123A1 Laminated semiconductor substrate, laminated chip package and method of manufacturing the same Public/Granted day:2011-12-29
Information query
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