Invention Grant
- Patent Title: Laminated semiconductor wafer, laminated chip package and method of manufacturing the same
- Patent Title (中): 层叠半导体晶片，层压芯片封装及其制造方法
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Application No.: US12848569Application Date: 2010-08-02
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Publication No.: US08426947B2Publication Date: 2013-04-23
- Inventor: Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima
- Applicant: Yoshitaka Sasaki , Hiroyuki Ito , Atsushi Iijima
- Applicant Address: US CA Milpitas CN Hong Kong
- Assignee: Headway Technologies, Inc.,SAE Magentics (H.K.) Ltd.
- Current Assignee: Headway Technologies, Inc.,SAE Magentics (H.K.) Ltd.
- Current Assignee Address: US CA Milpitas CN Hong Kong
- Agency: Oliff & Berridge, PLC
- Main IPC: H01L23/544
- IPC: H01L23/544
Abstract:
In a laminated semiconductor substrate, a plurality of semiconductor substrates are laminated. Each of the semiconductor substrate has a plurality of scribe-groove parts formed along scribe lines. Further, each of the semiconductor substrate has a plurality of device regions insulated from each other and has a semiconductor device formed therein. Further, an uppermost substrate and a lowermost substrate have an electromagnetic shielding layer formed using a ferromagnetic body. The electromagnetic shielding layer is formed in a shielding region except the extending zone. The extending zone is set a part which the wiring electrode crosses, in a peripheral edge part of the device region.
Public/Granted literature
- US20120025354A1 LAMINATED SEMICONDUCTOR SUBSTRATE, LAMINATED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME Public/Granted day:2012-02-02
Information query
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