Invention Grant
- Patent Title: Wafer level chip scale packaging
- Patent Title (中): 晶圆级芯片级封装
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Application No.: US11963690Application Date: 2007-12-21
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Publication No.: US08426960B2Publication Date: 2013-04-23
- Inventor: Ming Sun , Tao Feng , François Hébert , Yueh-Se Ho
- Applicant: Ming Sun , Tao Feng , François Hébert , Yueh-Se Ho
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: JDI Patent
- Agent Joshua D. Isenberg
- Main IPC: H01L23/48
- IPC: H01L23/48

Abstract:
A method for making back-to-front electrical connections in a wafer level chip scale packaging process is disclosed. A wafer containing a plurality of semiconductor chips is mounted on a package substrate. Each semiconductor chip in the plurality includes one or more electrodes on an exposed back side. Scribe lines between two or more adjacent chips on the wafer are removed to form relatively wide gaps. A conductive material is applied to the back side of the semiconductor chips and in the gaps. The conductive material in the gaps between two or more of the chips is then cut through leaving conductive material on the back side and on side walls of the two or more chips. As a result, the conductive material provides an electrical connection from the electrode on the back side of the chip to the front side of the chip.
Public/Granted literature
- US20090160045A1 WAFER LEVEL CHIP SCALE PACKAGING Public/Granted day:2009-06-25
Information query
IPC分类: