Invention Grant
- Patent Title: Buffer and display device
- Patent Title (中): 缓冲和显示设备
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Application No.: US12734691Application Date: 2008-08-19
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Publication No.: US08427206B2Publication Date: 2013-04-23
- Inventor: Etsuo Yamamoto , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shinsaku Shimizu
- Applicant: Etsuo Yamamoto , Yuhichiroh Murakami , Yasushi Sasaki , Seijirou Gyouten , Shinsaku Shimizu
- Applicant Address: JP Osaka
- Assignee: Sharp Kabushiki Kaisha
- Current Assignee: Sharp Kabushiki Kaisha
- Current Assignee Address: JP Osaka
- Agency: Harness, Dickey & Pierce
- Priority: JP2007-328945 20071220
- International Application: PCT/JP2008/064754 WO 20080819
- International Announcement: WO2009/081619 WO 20090702
- Main IPC: H03K3/00
- IPC: H03K3/00

Abstract:
A single-phase input including transistors all of which have only a single type of channel polarity, which buffer includes: a buffer section 32, including a first series circuit formed by two n-channel transistors connected to each other in series, a second series circuit formed by two n-channel transistors connected to each other in series at a connection point OUT, and a capacitor; and an inverted-signal generating section for generating an inverted-signal from an input signal, the inverted-signal generating section including n-channel transistors but no p-channel transistor, the input signal being inputted to respective gates of the transistors, the inverted-signal being inputted to a gate of the transistor 4, and an output signal being outputted via the connection point OUT. With the buffer, it is possible that a consumption current be reduced and a current drive for a load is enhanced.
Public/Granted literature
- US20100253393A1 BUFFER AND DISPLAY DEVICE Public/Granted day:2010-10-07
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