Sampling phase lock loop (PLL) with low power clock buffer

Invention Grant

US08427209B2 Sampling phase lock loop (PLL) with low power clock buffer 有权

Title translation: 具有低功耗时钟缓冲器的采样锁相环（PLL）

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Patent Title: Sampling phase lock loop (PLL) with low power clock buffer
Patent Title (中): 具有低功耗时钟缓冲器的采样锁相环（PLL）
Application No.: US13654051

Application Date: 2012-10-17
Publication No.: US08427209B2

Publication Date: 2013-04-23
Inventor: Xiang Gao , Ahmad Bahai , Mounir Bohsali , Ali Djabbari , Eric Klumperink , Bram Nauta , Gerard Socci
Applicant: National Semiconductor Corporation
Applicant Address: US CA Santa Clara
Assignee: National Semiconductor Corporation
Current Assignee: National Semiconductor Corporation
Current Assignee Address: US CA Santa Clara
Agent Andrew S. Viger; Wade J. Brady, III; Frederick J. Telecky, Jr.
Main IPC: H03L7/06
IPC: H03L7/06

Sampling phase lock loop (PLL) with low power clock buffer

Abstract:

A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up and pull-down transistors (and thereby the transitions of the sampling control signal) so that the transistors are not on at the same time.

Abstract(Chinese):

采样锁相环（PLL）电路包括被配置为将振荡器参考时钟转换为输入到采样相位检测器的方波采样控制信号的上拉/下降缓冲器。缓冲电路被配置为通过控制上拉和下拉晶体管的切换（以及因此采样控制信号的转换）来降低功率，使得晶体管不同时接通。

Public/Granted literature

US20130038365A1 Sampling Phase Lock Loop (PLL) With Low Power Clock Buffer Public/Granted day:2013-02-14

Information query

Espacenet

IPC分类:

H	电学
H03	基本电子电路
H03L	电子振荡器或脉冲发生器的自动控制、起振、同步或稳定（发电机的入H02P）
H03L7/00	频率或相位的自动控制；同步（一般谐振电路的调谐入H03J；数字通信系统中的同步见H04类中的有关各组）
H03L7/06	.应用加到频率或相位锁定环上的基准信号的