An information processing device includes: a first processing unit which asserts a first chip select signal or a second chip select signal in accordance with an address space to access; and a second processing unit accessible by the first processing unit by a first access method or a second access method, wherein when asserting the first chip select signal, the first processing unit accesses the second processing unit by the first access method, and when asserting the second chip select signal, the first processing unit accesses the second processing unit by the second access method.