Invention Grant
- Patent Title: Bit scan circuits and method in non-volatile memory
- Patent Title (中): 位扫描电路和方法在非易失性存储器中
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Application No.: US13164618Application Date: 2011-06-20
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Publication No.: US08427884B2Publication Date: 2013-04-23
- Inventor: Bo Liu , Jongmin Park , Chen Chen , Tien-chien Kuo
- Applicant: Bo Liu , Jongmin Park , Chen Chen , Tien-chien Kuo
- Applicant Address: US TX Plano
- Assignee: SanDisk Technologies, Inc.
- Current Assignee: SanDisk Technologies, Inc.
- Current Assignee Address: US TX Plano
- Agency: Davis Wright Tremaine LLP
- Main IPC: G11C7/10
- IPC: G11C7/10

Abstract:
A circuit for counting in an N-bit string a number of bits M, having a first binary value includes N latch circuits in a daisy chain where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to “interrogate” any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from “no-pass” to “pass” state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.
Public/Granted literature
- US20120321032A1 Bit Scan Circuits and Method in Non-volatile Memory Public/Granted day:2012-12-20
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