In one embodiment, a multi-stage decoder circuit is provided. Each stage of the decoder circuit is configured to perform one or more decoding iterations and produce an error mask indicating errors detected in the decoding stage. A compression circuit is coupled to one or more of the decoder stages and is configured to generate, for each of one or more of the plurality of decoder stages, a respective compressed error mask from the error mask produced by the decoder stage. A buffer circuit is coupled to the compression circuit and is configured to buffer the compressed error masks. A decompression circuit is coupled to the buffer circuit and is configured to decompress each of the compressed error masks. A combination circuit is coupled to the decompression circuit and is configured to combine the decompressed error masks into a single error mask.