Invention Grant
US08429487B2 Error protection method, TDC module, CTDC module, all-digital phase-locked loop, and calibration method thereof
有权
误差保护方法,TDC模块,CTDC模块,全数字锁相环及其校准方法
- Patent Title: Error protection method, TDC module, CTDC module, all-digital phase-locked loop, and calibration method thereof
- Patent Title (中): 误差保护方法,TDC模块,CTDC模块,全数字锁相环及其校准方法
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Application No.: US12982918Application Date: 2010-12-31
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Publication No.: US08429487B2Publication Date: 2013-04-23
- Inventor: Hsiang-Hui Chang , Bing-Yu Hsieh , Jing-Hong Conan Zhan
- Applicant: Hsiang-Hui Chang , Bing-Yu Hsieh , Jing-Hong Conan Zhan
- Applicant Address: TW Science-Based Industrial Park, Hsin-Chu
- Assignee: Mediatek Inc.
- Current Assignee: Mediatek Inc.
- Current Assignee Address: TW Science-Based Industrial Park, Hsin-Chu
- Agent Winston Hsu; Scott Margo
- Main IPC: H03M13/00
- IPC: H03M13/00

Abstract:
An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.
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