Invention Grant
- Patent Title: Semiconductor memory device and error correcting method
- Patent Title (中): 半导体存储器件和纠错方法
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Application No.: US12360215Application Date: 2009-01-27
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Publication No.: US08429496B2Publication Date: 2013-04-23
- Inventor: Yutaka Yamada , Tatsunori Kanai
- Applicant: Yutaka Yamada , Tatsunori Kanai
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2008-160685 20080619
- Main IPC: G11C29/00
- IPC: G11C29/00

Abstract:
A decoding unit is arranged between a reading unit that reads data with an error correction code added from memory cells on a specific one of the first data lines and an output unit that selectively outputs certain data of the read out data. The decoding unit corrects any errors in the data read out by the reading unit in accordance with the error correction code. The data in which the errors are corrected by the decoding unit is written back in the memory cells on the specific first data line.
Public/Granted literature
- US20090319870A1 SEMICONDUCTOR MEMORY DEVICE AND ERROR CORRECTING METHOD Public/Granted day:2009-12-24
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