Invention Grant
US08429594B2 Via design apparatus and via design method based on impedance calculations
有权
通过设计设计和基于阻抗计算的通孔设计方法
- Patent Title: Via design apparatus and via design method based on impedance calculations
- Patent Title (中): 通过设计设计和基于阻抗计算的通孔设计方法
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Application No.: US12781009Application Date: 2010-05-17
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Publication No.: US08429594B2Publication Date: 2013-04-23
- Inventor: Hirofumi Mori , Jun Yamada
- Applicant: Hirofumi Mori , Jun Yamada
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Staas & Halsey LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455 ; G06F7/60 ; G06F7/62
Abstract:
A via design apparatus includes a determination section that determines a value of a shape parameter indicating a shape of a via in a multilayer board. The via has a hole passing through the plurality of layers and a conductive section on a side wall of the hole. The apparatus also includes a calculation section that calculates a value of impedance of the via according to the value of the shape parameter.
Public/Granted literature
- US20100251200A1 VIA DESIGN APPARATUS AND VIA DESIGN METHOD Public/Granted day:2010-09-30
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