Invention Grant
US08435802B2 Conductor layout technique to reduce stress-induced void formations
有权
导体布置技术,以减少应力引起的空隙形成
- Patent Title: Conductor layout technique to reduce stress-induced void formations
- Patent Title (中): 导体布置技术,以减少应力引起的空隙形成
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Application No.: US11438127Application Date: 2006-05-22
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Publication No.: US08435802B2Publication Date: 2013-05-07
- Inventor: Min-Hwa Chi , Tai-Chun Huang , Chih-Hsiang Yao
- Applicant: Min-Hwa Chi , Tai-Chun Huang , Chih-Hsiang Yao
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A semiconductor device is prepared by an annealing process to interconnect at least two components of the device by a conductor line surrounded by an insulator material. The annealing process results in formation of residual stresses within the conductor line and the insulator material. A notch is designed in the layout on a selective portion of the mask for patterning conductor line. The existence of a shape of notch on the selective portion generates extra stress components within the conductor line than if without the existence of the notch. The position of the notch is selected so that the extra stress components substantially counteract the residual stresses, thereby causing a net reduction in the residual stresses. The reduction in the residual stresses results in a corresponding mechanical stress migration and therefore improvement in the reliability of the device.
Public/Granted literature
- US20070269907A1 Novel conductor layout technique to reduce stress-induced void formations Public/Granted day:2007-11-22
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