Invention Grant
- Patent Title: Vertical mirror in a silicon photonic circuit
- Patent Title (中): 硅光子电路中的垂直镜
-
Application No.: US12567601Application Date: 2009-09-25
-
Publication No.: US08435809B2Publication Date: 2013-05-07
- Inventor: John Heck , Ansheng Liu , Michael T. Morse , Haisheng Rong
- Applicant: John Heck , Ansheng Liu , Michael T. Morse , Haisheng Rong
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agent Kevin A. Reif
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A vertical total internal reflection (TIR) mirror and fabrication thereof is made by creating a re-entrant profile using crystallographic silicon etching. Starting with an SOI wafer, a deep silicon etch is used to expose the buried oxide layer, which is then wet-etched (in HF), opening the bottom surface of the Si device layer. This bottom silicon surface is then exposed so that in a crystallographic etch, the resulting shape is a re-entrant trapezoid with facets These facets can be used in conjunction with planar silicon waveguides to reflect the light upwards based on the TIR principle. Alternately, light can be coupled into the silicon waveguides from above the wafer for such purposes as wafer level testing.
Public/Granted literature
- US20110073972A1 VERTICAL MIRROR IN A SILICON PHOTONIC CIRCUIT Public/Granted day:2011-03-31
Information query
IPC分类: