Invention Grant
- Patent Title: Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods
-
Application No.: US13007002Application Date: 2011-01-14
-
Publication No.: US08435836B2Publication Date: 2013-05-07
- Inventor: Owen R. Fay , Warren M. Farnworth , David R. Hembree
- Applicant: Owen R. Fay , Warren M. Farnworth , David R. Hembree
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Perkins Coie LLP
- Main IPC: H01L21/50
- IPC: H01L21/50 ; H01L21/48 ; H01L21/44

Abstract:
Interconnect structures for stacked dies, including penetrating structures for through-silicon vias, and associated systems and methods are disclosed. A system in accordance with a particular embodiment includes a first semiconductor substrate having a first substrate material, and a penetrating structure carried by the first semiconductor substrate. The system further includes a second semiconductor substrate having a second substrate material with a preformed recess. The penetrating structure of the first semiconductor substrate is received in the recess of the second semiconductor substrate and is mechanically engaged with the recess and secured to the second semiconductor substrate.
Public/Granted literature
Information query
IPC分类: