Implementing semiconductor SoC with metal via gate node high performance stacked transistors

Invention Grant

US08435851B2 Implementing semiconductor SoC with metal via gate node high performance stacked transistors 有权

Title translation: 通过栅极节点高性能堆叠晶体管实现金属半导体SoC

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Patent Title: Implementing semiconductor SoC with metal via gate node high performance stacked transistors
Patent Title (中): 通过栅极节点高性能堆叠晶体管实现金属半导体SoC
Application No.: US13005089

Application Date: 2011-01-12
Publication No.: US08435851B2

Publication Date: 2013-05-07
Inventor: Karl R. Erickson , Phil C. Paone , David P. Paulsen , John E. Sheets, II , Gregory J. Uhlmann , Kelly L. Williams
Applicant: Karl R. Erickson , Phil C. Paone , David P. Paulsen , John E. Sheets, II , Gregory J. Uhlmann , Kelly L. Williams
Applicant Address: US NY Armonk
Assignee: International Business Machines Corporation
Current Assignee: International Business Machines Corporation
Current Assignee Address: US NY Armonk
Agent Joan Pennington
Main IPC: H01L21/8238
IPC: H01L21/8238

Implementing semiconductor SoC with metal via gate node high performance stacked transistors

Abstract:

A method and structures are provided for implementing metal via gate node high performance stacked vertical transistors in a back end of line (BEOL) on a semiconductor System on Chip (SoC). The high performance stacked vertical transistors include a pair of stacked vertical field effect transistors (FETs) formed by polycrystalline depositions in a stack between planes of a respective global signal routing wire. A channel length of each of the stacked vertical FETs is delineated by the polycrystalline depositions with sequential source deposition, channel deposition and drain deposition; and a wire via defines the gate node.

Abstract(Chinese):

提供了一种用于在半导体片上系统（SoC）上的后端（BEOL）中通过栅极节点高性能堆叠垂直晶体管实现金属的方法和结构。高性能堆叠垂直晶体管包括通过在相应的全局信号路由导线的平面之间的堆叠中的多晶沉积形成的一对堆叠垂直场效应晶体管（FET）。每个堆叠垂直FET的沟道长度由具有顺序源沉积，沟道沉积和漏极沉积的多晶沉积描绘; 并且导线通路限定栅极节点。

Public/Granted literature

US20120175626A1 IMPLEMENTING SEMICONDUCTOR SOC WITH METAL VIA GATE NODE HIGH PERFORMANCE STACKED TRANSISTORS Public/Granted day:2012-07-12

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS