Invention Grant
- Patent Title: Method of manufacturing super-junction semiconductor device
- Patent Title (中): 超结半导体器件的制造方法
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Application No.: US13110426Application Date: 2011-05-18
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Publication No.: US08435865B2Publication Date: 2013-05-07
- Inventor: Naoko Kodama
- Applicant: Naoko Kodama
- Applicant Address: JP Kawasaki
- Assignee: Fuji Electric Co., Ltd.
- Current Assignee: Fuji Electric Co., Ltd.
- Current Assignee Address: JP Kawasaki
- Priority: JP2010-116559 20100520
- Main IPC: H01L21/76
- IPC: H01L21/76 ; H01L21/425 ; H01L23/544

Abstract:
A method of manufacturing a super-junction semiconductor device facilitates suppressing the shape change caused in the alignment mark in the upper epitaxial layer transferred from the alignment mark in the lower epitaxial layer to be small enough to detect the transferred alignment mark with a few additional steps, even if the epitaxial layer growth rate is high. Alignment mark groups, each formed of trenches including parallel linear planar patterns and used in any of the multiple epitaxial layer growth cycles, are formed collectively on a scribe line between semiconductor chip sections; and the mesa region width between the trenches in each alignment mark group indicated by the distance between the single-headed arrows, facing opposite to each other and drawn in alignment mark groups is set to be one fourth of the designed total epitaxial layer thickness at the end of each epitaxial layer growth cycle or longer.
Public/Granted literature
- US20110287617A1 METHOD OF MANUFACTURING SUPER-JUNCTION SEMICONDUCTOR DEVICE Public/Granted day:2011-11-24
Information query
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