Invention Grant
- Patent Title: Semiconductor device including gate and three conductor electrodes
- Patent Title (中): 半导体器件包括栅极和三个导体电极
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Application No.: US13014060Application Date: 2011-01-26
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Publication No.: US08436431B2Publication Date: 2013-05-07
- Inventor: Yasuhiko Takemura
- Applicant: Yasuhiko Takemura
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Robinson Intellectual Property Law Office, P.C.
- Agent Eric J. Robinson
- Priority: JP2010-024580 20100205
- Main IPC: H01L29/78
- IPC: H01L29/78

Abstract:
An object is to provide a field effect transistor (FET) having a conductor-semiconductor junction, which has excellent characteristics, which can be manufactured through an easy process, or which enables high integration. Owing to the junction between a semiconductor layer and a conductor having a work function lower than the electron affinity of the semiconductor layer, a region into which carriers are injected from the conductor is formed in the semiconductor layer. Such a region is used as an offset region of the FET or a resistor of a semiconductor circuit such as an inverter. Further, in the case of setting up such an offset region and a resistor in one semiconductor layer, an integrated semiconductor device can be manufactured.
Public/Granted literature
- US20110193182A1 FIELD EFFECT TRANSISTOR AND SEMICONDUCTOR DEVICE Public/Granted day:2011-08-11
Information query
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