Invention Grant
US08436457B2 Stub minimization for multi-die wirebond assemblies with parallel windows
有权
具有平行窗口的多芯片焊接组件的短截线最小化
- Patent Title: Stub minimization for multi-die wirebond assemblies with parallel windows
- Patent Title (中): 具有平行窗口的多芯片焊接组件的短截线最小化
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Application No.: US13337565Application Date: 2011-12-27
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Publication No.: US08436457B2Publication Date: 2013-05-07
- Inventor: Richard Dewitt Crisp , Wael Zohni , Belgacem Haba , Frank Lambrecht
- Applicant: Richard Dewitt Crisp , Wael Zohni , Belgacem Haba , Frank Lambrecht
- Applicant Address: US CA San Jose
- Assignee: Invensas Corporation
- Current Assignee: Invensas Corporation
- Current Assignee Address: US CA San Jose
- Agency: Lerner, David, Littenberg, Krumholz & Mentlik, LLP
- Main IPC: H01L21/02
- IPC: H01L21/02

Abstract:
A microelectronic package can include a substrate having first and second opposed surfaces and first and second apertures extending between the first and second surfaces, first and second microelectronic elements each having a surface facing the first surface of the substrate, a plurality of terminals exposed at the second surface in a central region thereof, and leads electrically connected between contacts of each microelectronic element and the terminals. The apertures can have first and second parallel axes extending in directions of the lengths of the respective apertures. The second surface can have a central region disposed between the first and second axes. Each microelectronic element can embody a greater number of active devices to provide memory storage array function than any other function. The terminals can be configured to carry all of the address signals transferred to the microelectronic package.
Public/Granted literature
- US20130082394A1 STUB MINIMIZATION FOR MULTI-DIE WIREBOND ASSEMBLIES WITH PARALLEL WINDOWS Public/Granted day:2013-04-04
Information query
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