A multiple level integrated circuit uses an array of oppositely oriented individually enabled buffers between through-silicon vias (TSVs) and a clocked flip-flop, for each of multiple signal lines that include TSVs. Applying and/or reading logic levels to and from the TSVs and associated flip-flops produces values that a logic element compares to expected values characterizing nominal operation or detects open and short circuit defects. A process associated with testing the TSVs during assembly comprises testing for short circuits and then exposing and connecting the TSVs via a conductive layer to check for open circuits.