According to one embodiment, a semiconductor storage device includes memory cells including serially-connected variable-resistance layer and diode. A memory cell array includes the memory cells arranged on a plane including a first and second axes and has a first region lying along an edge of the array and a second region lying opposite to the edge with respect to the first region. A first wiring is continuous along the first axis between both ends of the array, partly lies in the second region, and is connected to the first ends of the memory cells. A second wiring lies along the first axis only in the first region, is connected to the first ends of the memory cells, and is divided between adjacent memory cells. A third wiring is continuous along the second axis between both ends of the array, and connected to the second ends of the memory cells.