Invention Grant
US08437181B2 Shared bit line SMT MRAM array with shunting transistors between the bit lines
有权
共享位线SMT MRAM阵列，在位线之间分流晶体管
- Patent Title: Shared bit line SMT MRAM array with shunting transistors between the bit lines
- Patent Title (中): 共享位线SMT MRAM阵列，在位线之间分流晶体管
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Application No.: US12803523Application Date: 2010-06-29
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Publication No.: US08437181B2Publication Date: 2013-05-07
- Inventor: Hsu Kai Yang , Yutaka Nakamura , John Debrosse
- Applicant: Hsu Kai Yang , Yutaka Nakamura , John Debrosse
- Applicant Address: US CA Milpitas US NY Yorktown Heights
- Assignee: MagIC Technologies, Inc.,International Business Machines Corporation
- Current Assignee: MagIC Technologies, Inc.,International Business Machines Corporation
- Current Assignee Address: US CA Milpitas US NY Yorktown Heights
- Agency: Saile Ackerman LLC
- Agent Stephen B. Ackerman; Billy Knowles
- Main IPC: G11C11/00
- IPC: G11C11/00
Abstract:
An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.
Public/Granted literature
- US20110317479A1 Shared bit line SMT MRAM array with shunting transistors between the bit lines Public/Granted day:2011-12-29
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