Invention Grant
- Patent Title: Methods for improved simulation of integrated circuit designs
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Application No.: US12082971Application Date: 2008-04-14
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Publication No.: US08438003B2Publication Date: 2013-05-07
- Inventor: Rakesh Agarwal , Oana Baltaretu
- Applicant: Rakesh Agarwal , Oana Baltaretu
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Sawyer Law Group, P.C.
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A method of improved simulator processing is provided. The method according to the current invention includes grouping frequently accessed data into one set id to improve memory hierarchy performance. The method further includes simulating predication in a non-predicated architecture to improve CPU performance. The simulated predication includes pseudo-predicated implementation of read-operation vector element access pseudo-predicated implementation of write-operation vector element access, and predicated implementation of multi-way branches with assignment statements having a same left-hand-side (lhs). The method further includes determining a selection path in a multi-sensitive “always” block to reduce taken branches. The multi-sensitive “always” block selection path determination includes generating instance-specific code to save port allocation storage, and generating inlined instance-specific code to combine sensitive actions. The method further includes regenerating code affected by the assignment statement to implement value-change callback.
Public/Granted literature
- US20090037161A1 Methods for improved simulation of integrated circuit designs Public/Granted day:2009-02-05
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