Invention Grant
US08438320B2 Various methods and apparatus for address tiling and channel interleaving throughout the integrated system
有权
用于整个集成系统中的地址拼接和信道交织的各种方法和装置
- Patent Title: Various methods and apparatus for address tiling and channel interleaving throughout the integrated system
- Patent Title (中): 用于整个集成系统中的地址拼接和信道交织的各种方法和装置
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Application No.: US12573669Application Date: 2009-10-05
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Publication No.: US08438320B2Publication Date: 2013-05-07
- Inventor: Krishnan Srinivasan , Drew E. Wingard , Chien-Chun Chou
- Applicant: Krishnan Srinivasan , Drew E. Wingard , Chien-Chun Chou
- Applicant Address: US CA Milpitas
- Assignee: Sonics, Inc.
- Current Assignee: Sonics, Inc.
- Current Assignee Address: US CA Milpitas
- Agency: Rutan & Tucker, LLP
- Main IPC: G06F13/00
- IPC: G06F13/00
Abstract:
Various methods and apparatus are described for a target with multiple channels. Address decoding logic is configured to implement a distribution of requests from individual burst requests to two or more memory channels making up an aggregate target. The address decoding logic implements a channel-selection hash function to allow requests from each individual burst request to be distributed amongst the two or more channels in a non-linear sequential pattern in channel round order that make up the aggregate target.
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