Invention Grant
- Patent Title: Semiconductor integrated circuit for minimizing a deviation of an internal power supply from a desired value
- Patent Title (中): 半导体集成电路,用于最小化内部电源与期望值的偏差
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Application No.: US13317847Application Date: 2011-10-31
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Publication No.: US08438406B2Publication Date: 2013-05-07
- Inventor: Shingo Nakashima
- Applicant: Shingo Nakashima
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: McGinn IP Law Group, PLLC
- Priority: JP2005-328519 20051114
- Main IPC: G06F1/00
- IPC: G06F1/00 ; G06F11/30 ; G05F3/02

Abstract:
A semiconductor integrated circuit includes first and second external terminals receiving an external power supply voltage, an internal power supply line coupling to the first and second external terminals, a first transistor coupling between the first external terminal and the internal power supply line, a second transistor that is coupled between the second external terminal and the internal power supply line, a first monitor line coupling to a first node of the internal power supply line, a second monitor line coupling to a second node of the internal power supply line, the second node being different from the first node, and a controller coupling to the first and second monitor lines, the controller outputs a control signal corresponding to potentials of the first and second monitor lines to the first and second transistors.
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