Invention Grant
US08438434B2 N-way parallel turbo decoder architecture 有权
N路并行turbo解码器架构

  • Patent Title: N-way parallel turbo decoder architecture
  • Patent Title (中): N路并行turbo解码器架构
  • Application No.: US12650072
    Application Date: 2009-12-30
  • Publication No.: US08438434B2
    Publication Date: 2013-05-07
  • Inventor: Nur Engin
  • Applicant: Nur Engin
  • Applicant Address: NL Eindhoven
  • Assignee: NXP B.V.
  • Current Assignee: NXP B.V.
  • Current Assignee Address: NL Eindhoven
  • Main IPC: G06F11/00
  • IPC: G06F11/00
N-way parallel turbo decoder architecture
Abstract:
Various embodiments relate to a memory device in a turbo decoder and a related method for allocating data into the memory device. Different communications standards use data blocks of varying sizes when enacting block decoding of concatenated convolutional codes. The memory device efficiently minimizes space while enabling a higher throughput of the turbo decoder by enabling a plurality of memory banks of equal size. The number of memory banks may be limited by the amount of unused space in the memory banks, which may be a waste of area on an IC chip. Using the address associated with the maximum value of the data block, the memory may be split into a plurality of memory blocks according to the most-significant bits of the maximum address, with a number of parallel SISO decoders matching the number of memory banks. This may enable higher throughput while minimizing area on the IC chip.
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