Invention Grant
- Patent Title: Method for testing an address bus in a logic module
- Patent Title (中): 在逻辑模块中测试地址总线的方法
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Application No.: US12738253Application Date: 2008-09-10
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Publication No.: US08438435B2Publication Date: 2013-05-07
- Inventor: Thomas Schneider , Peter Wirth , Otto Pfitzer
- Applicant: Thomas Schneider , Peter Wirth , Otto Pfitzer
- Applicant Address: DE Stuttgart
- Assignee: Robert Bosch GmbH
- Current Assignee: Robert Bosch GmbH
- Current Assignee Address: DE Stuttgart
- Agency: Kenyon & Kenyon LLP
- Priority: DE102007049354 20071015
- International Application: PCT/EP2008/061998 WO 20080910
- International Announcement: WO2009/049970 WO 20090423
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
In a method for testing an address bus in a logic module, a logic module, a computer program and a computer program product, the method provides for a logic module to have at least one data register, into which addresses detected by the address decoder are written.
Public/Granted literature
- US20110202803A1 METHOD FOR TESTING AN ADDRESS BUS IN A LOGIC MODULE Public/Granted day:2011-08-18
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