Invention Grant
- Patent Title: Poison bit error checking code scheme
- Patent Title (中): 毒码错误检查码方案
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Application No.: US12317849Application Date: 2008-12-29
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Publication No.: US08438452B2Publication Date: 2013-05-07
- Inventor: Rajat Agarwal , Scott Huddleston , Dennis Brzezinski
- Applicant: Rajat Agarwal , Scott Huddleston , Dennis Brzezinski
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Caven & Aghevli LLC
- Main IPC: G06F11/00
- IPC: G06F11/00

Abstract:
In one embodiment, a method provides determining one of an occurrence and a non-occurrence of an event, the one of the occurrence and the non-occurrence resulting in an event determination; and processing a code having an event bit, said processing in accordance with the determination and the code, by determining if the event bit corresponds to the event determination, and if the event bit does not correspond to the event determination, encoding the code to generate a poison bit that corresponds to the event determination.
Public/Granted literature
- US20100169739A1 Poison bit error checking code scheme Public/Granted day:2010-07-01
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