Invention Grant
- Patent Title: Hierarchical editing of printed circuit board pin assignment
- Patent Title (中): 印刷电路板引脚分配的分层编辑
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Application No.: US12650352Application Date: 2009-12-30
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Publication No.: US08438524B1Publication Date: 2013-05-07
- Inventor: Vikas Kohli , Steven R. Durrill
- Applicant: Vikas Kohli , Steven R. Durrill
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Holland & Knight LLP
- Agent Mark H. Whittenberger
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
An interface object library tool for manipulating interface objects for a printed circuit board (PCB) tool is disclosed. The interface object library tool includes a hierarchical interface display module, an input module, and a store. The hierarchical interface display module is configured to display an interrelation between a plurality of interface objects and a plurality of groups each including a plurality of signal, power and ground lines. The plurality of interface objects are configured to be associated with a plurality of block objects to define a plurality of component objects. The input module is configured to: accept association of the plurality of groups and the plurality of signal, power and ground lines without defining pin or pad assignments; and accept association between the plurality of interface objects and a plurality of groups. The store is configured to retain the plurality of interface objects; the plurality of groups; the plurality of signal, power and ground lines; and associations between these three.
Information query