Invention Grant
- Patent Title: Stacking apparatus and method for stacking integrated circuit elements
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Application No.: US13359155Application Date: 2012-01-26
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Publication No.: US08440472B2Publication Date: 2013-05-14
- Inventor: Kazuya Okamoto
- Applicant: Kazuya Okamoto
- Applicant Address: JP Tokyo
- Assignee: Nikon Corporation
- Current Assignee: Nikon Corporation
- Current Assignee Address: JP Tokyo
- Agency: Morgan, Lewis & Bockius LLP
- Priority: JP2004-002081 20040107
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A stacking apparatus that stacks chip assemblies each having a plurality of chips disposed continuously with circuit patterns and electrodes, includes: a plurality of stages each allowed to move arbitrarily, on which the chip assemblies are placed; a storage unit that stores an estimated extent of change in a position of an electrode at each chip, expected to occur as heat is applied to the chip assemblies placed on the plurality of stages during a stacking process; and a control unit that sets positions of the plurality of stages to be assumed relative to each other during the stacking process based upon the estimated extent of change in the position of the electrode at each chip provided from the storage unit and position information indicating positions of individual chips formed at the chip assemblies and controls at least one of the plurality of stages.
Public/Granted literature
- US20120118477A1 STACKING APPARATUS AND METHOD FOR STACKING INTEGRATED CIRCUIT ELEMENTS Public/Granted day:2012-05-17
Information query
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