Invention Grant
US08441110B1 Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
有权
侧面引线,底部裸露焊盘和底部裸露引线熔合四边形半导体封装
- Patent Title: Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package
- Patent Title (中): 侧面引线,底部裸露焊盘和底部裸露引线熔合四边形半导体封装
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Application No.: US13109845Application Date: 2011-05-17
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Publication No.: US08441110B1Publication Date: 2013-05-14
- Inventor: Yeon Ho Choi
- Applicant: Yeon Ho Choi
- Applicant Address: US AZ Chandler
- Assignee: Amkor Technology, Inc.
- Current Assignee: Amkor Technology, Inc.
- Current Assignee Address: US AZ Chandler
- Main IPC: H01L23/495
- IPC: H01L23/495

Abstract:
A semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and a plurality of leads which are segregated into at least two concentric rows. Connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of the leads of each row. At least portions of the die paddle, the leads, and the semiconductor die are encapsulated by a package body, the bottom surfaces of the die paddle and the leads of at least one row thereof being exposed in a common exterior surface of the package body.
Information query
IPC分类: