Invention Grant
US08441278B2 Stacked semiconductor device and method of connection test in the same
有权
堆叠的半导体器件和连接方法的测试相同
- Patent Title: Stacked semiconductor device and method of connection test in the same
- Patent Title (中): 堆叠的半导体器件和连接方法的测试相同
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Application No.: US12882615Application Date: 2010-09-15
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Publication No.: US08441278B2Publication Date: 2013-05-14
- Inventor: Norio Yamanishi , Shinobu Kurosaka
- Applicant: Norio Yamanishi , Shinobu Kurosaka
- Applicant Address: JP Nagano-Shi
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-Shi
- Agency: Kratz, Quintos & Hanson, LLP
- Priority: JP2009-223774 20090929
- Main IPC: G01R31/02
- IPC: G01R31/02

Abstract:
A stacked semiconductor device includes a first semiconductor device equipped with a first semiconductor chip 14 having a transistor circuit and protection diodes, and a second semiconductor device equipped with a second semiconductor chip 24 having a transistor circuit and protection diodes, and stacked on the first semiconductor device via a connection portion, wherein a power supply line connected to the first and second semiconductor chips is used in common, and a forward ON voltage of the protection diodes of the first semiconductor chip is set higher than a forward ON voltage of the protection diodes of the second semiconductor chip 24. When a connection test is executed, the forward ON voltage of the protection diodes of the first semiconductor chip or the second semiconductor chip is detected and then normal/open is judged.
Public/Granted literature
- US20110074438A1 STACKED SEMICONDUCTOR DEVICE AND METHOD OF CONNECTION TEST IN THE SAME Public/Granted day:2011-03-31
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