Invention Grant
- Patent Title: Impedance calibration circuit and impedance calibration method
- Patent Title (中): 阻抗校准电路和阻抗校准方法
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Application No.: US13187603Application Date: 2011-07-21
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Publication No.: US08441282B2Publication Date: 2013-05-14
- Inventor: Mi Hye Kim
- Applicant: Mi Hye Kim
- Applicant Address: KR Gyeonggi-do
- Assignee: SK Hynix Inc.
- Current Assignee: SK Hynix Inc.
- Current Assignee Address: KR Gyeonggi-do
- Agency: William Park & Associates Patent Ltd.
- Priority: KR10-2010-0126444 20101210
- Main IPC: H03K19/003
- IPC: H03K19/003

Abstract:
An integrated circuit includes a first ODT (On Die Termination) unit and an input buffer. The first ODT unit is configured to receive at least one pull-up code and at least one pull-down code and calibrate a resistance value for impedance matching of a first line transferring data. The input buffer is configured to buffer the data in response to a reference voltage level and drive input data. Herein, the driving of the input data is controlled in response to the pull-up code and the pull-down code.
Public/Granted literature
- US20120146687A1 IMPEDANCE CALIBRATION CIRCUIT AND IMPEDANCE CALIBRATION METHOD Public/Granted day:2012-06-14
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