Invention Grant
US08441285B2 Latching control buffer between functional logic and tri-state output buffer
失效
功能逻辑和三态输出缓冲器之间的锁存控制缓冲器
- Patent Title: Latching control buffer between functional logic and tri-state output buffer
- Patent Title (中): 功能逻辑和三态输出缓冲器之间的锁存控制缓冲器
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Application No.: US13286423Application Date: 2011-11-01
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Publication No.: US08441285B2Publication Date: 2013-05-14
- Inventor: Lee D. Whetsel
- Applicant: Lee D. Whetsel
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: H03K19/173
- IPC: H03K19/173
Abstract:
An electronic integrated circuit includes a signal path connected between the functional logic (15) thereof and an external output terminal. The signal path includes a switch (S), a bus holder circuit (121B), and an output buffer (19).
Public/Granted literature
- US20120043992A1 IC OUTPUT SIGNAL PATH WITH SWITCH, BUS HOLDER, AND BUFFER Public/Granted day:2012-02-23
Information query
IPC分类:
