A gate driver includes a shift register, a logic control circuit, and an output enable control circuit. The shift register generates a plurality of scan signals according to a vertical synchronous signal and a vertical clock signal. The output enable control circuit generates a second output enable signal according to the vertical synchronous signal, the vertical clock signal, and an output enable signal. After the vertical synchronous signal and the vertical clock signal are both triggered together for two times, the second output enable converts from a high level to a low level. The logic control circuit outputs the plurality of scan signals when the second output enable signal is at the low level.