Invention Grant
US08441830B2 Manufacturing method for stacking memory circuits and for addressing a memory circuit, corresponding stacking and device
失效
用于堆叠存储器电路和寻址存储器电路的制造方法，相应的堆叠和器件
- Patent Title: Manufacturing method for stacking memory circuits and for addressing a memory circuit, corresponding stacking and device
- Patent Title (中): 用于堆叠存储器电路和寻址存储器电路的制造方法，相应的堆叠和器件
-
Application No.: US12919799Application Date: 2009-02-23
-
Publication No.: US08441830B2Publication Date: 2013-05-14
- Inventor: Pierre Gravez , Michel Thill
- Applicant: Pierre Gravez , Michel Thill
- Applicant Address: FR Meudon
- Assignee: Gemalto SA
- Current Assignee: Gemalto SA
- Current Assignee Address: FR Meudon
- Agency: Buchanan Ingersoll & Rooney PC
- Priority: EP08305050 20080307
- International Application: PCT/EP2009/052121 WO 20090223
- International Announcement: WO2009/112354 WO 20090917
- Main IPC: G11C5/02
- IPC: G11C5/02
Abstract:
The invention relates to a method for making a stack of memory circuits, wherein the method includes the step of testing the validity of at least two memory circuits. According to the invention, the method includes the phase of configuring each memory circuit, the configuration phase including the step of writing, within a configuration device of each memory circuit included in the stack, a piece of information on an identifier allocated to the memory circuit in the stack, and a piece of information on the results of the validity test of the memory circuit. The invention also relates to a method for addressing a memory circuit, to a stack of memory circuits, and to an electronic device including such a stack.
Public/Granted literature
Information query
