Invention Grant
- Patent Title: Semiconductor storage circuit
- Patent Title (中): 半导体存储电路
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Application No.: US13033181Application Date: 2011-02-23
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Publication No.: US08441851B2Publication Date: 2013-05-14
- Inventor: Nobukazu Murata
- Applicant: Nobukazu Murata
- Applicant Address: JP
- Assignee: Lapis Semiconductor Co., Ltd.
- Current Assignee: Lapis Semiconductor Co., Ltd.
- Current Assignee Address: JP
- Agency: Rabin & Berdo, P.C.
- Priority: JP2010-039210 20100224
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
The present invention provides a semiconductor storage circuit that may suppress a data read characteristic from being deteriorated due to influence of characteristic change of a sense amplifier, in a multi-bit-type memory cell. The semiconductor storage circuit includes a memory cell array that has plural multi-bit-type memory cells, two multiplexers, and two sense amplifiers. The first multiplexer connects a main bit line connected to an R-side electrode of the even-numbered memory cell in a row direction to the first sense amplifier, and connects a main bit line connected to an L-side electrode of the odd-numbered memory cell to the second sense amplifier. The second multiplexer connects a main bit line connected to an L-side electrode of the even-numbered memory cell to the first sense amplifier, and connects a main bit line connected to an R-side electrode of the odd-numbered memory cell to the second sense amplifier.
Public/Granted literature
- US20110205776A1 SEMICONDUCTOR STORAGE CIRCUIT Public/Granted day:2011-08-25
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