A frequency divider with a twenty-five percent duty cycle is disclosed. A frequency divider may include an input configured to receive a clock signal, each cycle of the clock signal including a first phase and a second phase, a plurality of latches, and a plurality of three-state circuits wherein a first of the plurality of three-state circuits is configured to drive a first twenty-five percent duty cycle signal from within the first three-state circuit high during a first phase of a first of two clock cycles.